Structured silicon anode

ABSTRACT

A silicon/lithium battery can be fabricated from a silicon substrate. This allows the battery to be produced as an integrated unit on a chip. The battery includes a silicon anode formed from submicron diameter pillars of silicon fabricated on an n-type silicon wafer. The battery also includes a cathode including lithium.

This application is a division of U.S. application Ser. No. 10/533,822filed on Aug. 31, 2005 now U.S. Pat. No. 7,402,829 which is stillpending and the disclosure of which is incorporated hereinto in itsentirety by reference. The parent U.S. application is, in turn, theentry into the national phase in the U.S. of International ApplicationSerial No. PCT/GB2003/004783 which was filed on 5 Nov. 2003. TheInternational Application claims priority from British Application No.GB 0225779.8 filed on 5 Nov. 2002.

The present invention relates to structured silicon anodes for lithiumbattery applications.

Silicon is recognised as a potentially high energy per unit volume hostmaterial for lithium in lithium battery applications¹. Attempts atrealising this potential have met with only partial success whennano-composites of silicon powder and carbon black have been used². Themajor technical problem associated with the use of silicon/lithiumappears to be the mechanical failure brought about by the repeated largevolume expansion associated with alloying^(1c,3). Metallic andintermetallic anodic host materials, other than layer materials such asgraphite, are reported to disintegrate after a few lithiuminsertion/extraction cycles^(3,4) unless in fine powder form (sub-micronrange). Since we are interested in finding a way to make a lithiumbattery integrated onto a silicon chip we need to find a solution tothis materials problem. It is envisaged that the principal applicationsarea for lithium batteries integrated into a chip would be in themedical field. Thus the well-developed practice of cochlea implantsappears to be an area that would benefit from an integrated batterysupply⁵.

This invention seeks to realise the potential of the silicon-lithiumsystem to allow the possibility of a lithium battery integrated on to asilicon chip.

Accordingly this invention provides a method of fabricating sub-micronsilicon electrode structures on a silicon wafer. Preferably thesestructures comprise pillars.

For a silicon-lithium system the basic cell diagram can be representedas Li|Li⁺-electrolyte|Si, for this cell the cathodic process is,discharge of lithium onto silicon to form an alloy (charging), and theanodic process is lithium extraction or de-alloying (discharging). TheEMF data reported by Wen and Huggins⁶ for the liquid system at 415° C.is shown bracketed below and the solid system at room temperature⁷ isshown un-bracketed below. Their results (in mV vs, Li) are:Si/Li₁₂Si₇-582 (332); Li₁₂Si₇/Li₇Si₃-520 (288); Li₇Si₃/Li₁₃Si₄-428(158); Li₁₃Si₄/Li₂₁Si₅-˜300 (44).

It will be appreciated that the formation of Li₁₂Si₇ in place of Siresults in a significant volume change (the alloy is 2.17 times bigger).On a conventional silicon wafer suitable for use as an anode for alithium battery this volume change leads to crack formation andpulverisation however due to their small size and configurationsub-micron anode structures made in accordance with the invention, arebe able to tolerate the conditions occasioned by the massive volumechanges occasioned by lithium alloying/de-alloying.

In tests structured electrodes of sub micron diameter Si pillarsmaintained their structural integrity throughout the cycling whereasplanar Si electrodes showed cracks (2 micron features) after 50 cycles.An appropriate size restriction to achieve suitable electrodes is thatthe silicon pillars should not exceed a fractional surface coverage (F)of ˜0.5.

An embodiment of the invention will now be described by way ofnon-limiting example only, with reference to the accompanying drawings,in which:

FIG. 1 is a schematic view of a structured electrode;

FIG. 2 shows one of a series of CV scan sets;

FIG. 3 shows results for a series of galvanostratic measurements;

FIG. 4 shows pictures of the structure;

FIG. 5 shows SEM pictures of the structure; and

FIG. 6 shows a lithium battery in accordance with the present invention.

The electrochemical discharge of lithium on silicon and its subsequentchemical reaction destroys the silicon lattice, giving rise to theswelling of the solid, producing amorphous Si/Li phases¹³. The first newphase to appear in the system is Li₁₂Si₇. This compound, and all therest up to Li, is a so-called Zintl-Phase Compound (ZPC), and consistsof simple, electropositive, cations and complex co-valently bound,multiply charged, electronegative, anions. Of course the charge ascribedto the “ions” is purely notional: the actual charge (depending upondefinition) is less than the formal value and may be considerably less,hence the bulk lithium will be referred to as Li^(o) and bulk silicon asSi_(n) ^(o).

It is important to form some idea of the mechanism of lithiation andde-lithiation of silicon. It is proposed that:

(i) Discharged lithium reacts with silicon forming a ZPC film withatomically continuous contact to the silicon.

(ii) Lithium excess diffuses (via a vacancy mechanism) through thecompact ZPC film to react with silicon at the Si/ZPC interface,thickening the ZPC film, without void formation.

These processes might be represented by: Li⁺(e1)+e⁻ (solid)→Li(ads.);Li(ads.)+V(ZPC)→Li^(o) (ZPC)_(s); Li^(o) (ZPC)_(s)→diffusion→Li^(o)(ZPC)_(ZPC/si); x Li^(o)+ySi^(o)→ZPC (Li_(x/y)Si)

(Li(ads) is Li adsorbed on ZPC; V is a Li^(o) vacancy in ZPC)

(iii) The amorphous¹³ ZPC film is deformable and so does not give riseto significant stress induced cracking on volume change.

The diffusion coefficient, D, for Li in crystalline Si¹⁴ is ˜10⁻¹⁴ cm²s⁻¹, Li in ZPC is expected to be faster; a value of D 10⁻¹² cm² s⁻¹would be enough to account for all the processes carried out in thisstudy. This model for ZPC film formation is in many ways analogous tothe model of SiO₂ layer formation on silicon due to Deal and Grove¹⁵:but the details are different and will be treated elsewhere.

The model for ZPC decomposition is, in broad terms, the reverse of theabove steps. Discharge of Li^(o) at the electrolyte interface produces asurface vacancy in the ZPC. Locally Li^(o) moves into the vacancy so thevacancy diffuses back to the ZPC/Si interface: at the interface Si_(n)rejoins the Si phase (where it is said to be polycrystalline¹³) andvacancies coalesce to produce larger void spaces. These spaces, as theycoalesce further and grow, give rise to the crack like features seen inthe SEM pictures in FIGS. 4 c,d and 5. Such a process has been describedby Beaulieu et al¹⁶ for lithium removal from silicon/tin alloys.

It has been shown that repeated Li alloying/de-alloying of planar Si canbe carried out without pulverisation of the substrate, cf. FIG. 5.However, as noted, the alloy/de-alloy process is limited by diffusionthrough the ZPC layer. In order to obtain charging rates suitable forvarious applications it is necessary to increase the surface area of theSi/electrolyte interface; and this has been done using pillarfabrication. Previous attempts using silicon particles have failedbecause the particle-to-particle contacts change and part with cycling².The pillar structures, on the other hand, are largely maintained asevidenced by the flatness of the pillar tops after 50 cycles, cf. FIG.4.

Efficiencies of <100% reported here are attributed mainly to reaction,on alloying, with the electrolyte, and to a lesser extent isolation ofregions of ZPC. The data presented here show that reduced currentdensity on both alloying and de-alloying results in improvingefficiency. It is supposed that this improvement comes mainly from areduced surface concentration of adsorbed Li on alloying and accessingall the lithium in the ZPC on de-alloying.

There is large scope for further increasing the surface-to-volume ratioof the pillar construction, for example, pillars of diameter (d) ˜0.3microns and 6 micron height (H). The pillar volume (v) would be, FH, andfor F=0.4, v=2.4×10⁻⁴ cc/cm², which is equivalent, when converted toLi₁₂Si₇, to a capacity of 3.81×10³v=914 microAhrcm⁻². The surface areaof such a pillar structure is ˜4 FH/d, which is the basis of the muchimproved characteristics.

To make structures in accordance with the invention the following methodmay be used, namely “Island Lithography” as disclosed in internationalpatent No. WO01/13414. This method employs cesium chloride as the resistin the lithographic step in the fabrication of pillar arrays. It worksas follows. A thin film of CsCl is vacuum deposited on the clean,hydrophilic, surface of the Si substrate. This system is then exposed tothe atmosphere at a controlled relative humidity. A multilayer of wateradsorbes on the surface, the CsCl is soluble in the water layer (beingmore soluble at places of higher radius of curvature). The CsClre-organises into a distribution of hemispherical islands, driven by theexcess surface energy associated with CsCl surface curvature. Sucharrays are useful in making structures for various studies involvingnano-scale phenomena. In this case reactive ion etching is preferablyused, with the islands acting as X masks so that removal of thesurrounding silicon forms the desired pillar structures.

A study of the kinetics of the formation of island arrays has beencarried out on GaAs surfaces⁹ and more recently, and more extensively,on Si/SiO₂ surfaces¹⁰ where the technique and results are described indetail. The process variables are: CsCl film thickness (L); humidity(RH), time of exposure (t). The resulting island array has a Gaussiandistribution of diameters, average diameter (<d>) standard deviation(±s) and surface fractional coverage (F). Having made the CsCl resistarray the next step is reactive ion etching (RIE) to produce thecorresponding array of pillars¹¹. The RIE process variables are:feed-gas composition, flow rate and chamber pressure; RF power; dc bias;etch time. The results are characterised by the etch depth,corresponding to pillar height (H), and the wall angle, namely the anglethat the pillar wall makes with the wafer plane; it is chosen in thisstudy to be close to 90°. The examples reported in this work were etchedin a Oxford Plasmalab 80 apparatus. The etch gas was (O₂:Ar: CHF₃) inthe ratio 1:10:20; feed rate 20 sccm; chamber pressure, 50 millipascals; RF power, 73 watts; dc bias 200V.

The pillar structure reported in this study (K-series) was characterisedas <d>=580 nm±15 nm; F=0.34; H=810 nm: it was made using, L=80 nm;RH=40%; t=17.5 hrs. After fabrication the silicon samples were washed inwater; etched for 20 seconds in NH₄OH(28 w % NH₃):H₂O₂(100 v/v):H₂O inequal volume ratios; the etchant was flooded away with de-ionized waterand blow dried.

Of course the structures may also be fabricated by other knowntechniques, such as photolithography, which produce regular arrays offeatures rather than the scattered distribution produced by islandlithography.

FIG. 1 is a schematic view of a structured electrode, in accordance withthe invention and as used in the following tests, it shows a partsectional view of the anode in which the pillars 2 can clearly be seenon the silicon wafer 3.

FIG. 6 shows a lithium battery, comprising a typical embodiment of thepresent invention, and including an anode 1, a cathode 4, a polymerelectrolyte 5, a first strip 6 representing a rectifier circuitconnected to a coil encircling the anode for charging purposes, a secondstrip 7 representing the output circuit (driven by the battery), and apair of wires 8 for connection to the device to be driven.

Electrochemical tests were performed in a three-electrode, glass, cellwhere the Si sample is the working electrode and metallic Li is used forboth the counter and reference electrodes. A 1 M solution of LiClO₄(Merck Selectipurâ) in ethylene carbonate:diethyl carbonate (MerckSelectipurâ), (1:1) w/w solvent was used as the electrolyte. The cellwas assembled under a dry argon atmosphere in a glove box. Ohmic contactwas made to the rear side of the silicon samples electrodes using a 1:1In—Ga eutectic alloy¹². The electrode area was delineated using anO-ring configuration in a PTFE holder. No adhesive is used and a goodelectrolyte/atmosphere seal is obtained. In an earlier study we foundthat epoxy adhesive, used to mount a Si electrode, contaminated theactive electrode surface causing spurious currents at high voltages(>2V).

Electrochemical behaviour of the cell was investigated by cyclicvoltammetry (CV) and by galvanostatic measurement (voltage vs. time atconstant current), using an electrochemical workstation (VMPPerkinElmer™ Instruments). The capacity referred to here is the totalcharge inserted into the projected electrode surface area exposed to theelectrolyte (this ignores any surface area due to structuring), given asmAhcm⁻² (micro Amp hours cm⁻²).

The results obtained were:

The response of the Li|Li⁺-electrolyte|Si cell was measured: for thiscell the cathodic process is, discharge of lithium onto silicon to forman alloy (charging), and the anodic process is lithium extraction orde-alloying (discharging). FIG. 2 shows one series of CV scan sets(details in caption). The first cycle, and to quite a large extent thesecond, differs from those that follow. It is conjectured that thisdifference is due to a “formation” effect, associated with the filmingof the electrode during the first Li discharge. After the first andsecond cycles, the scans assume a repeatable general shape. Since theseare scans in which the potential is changed slowly and the currentdensities are therefore small, there are no IR drop or diffusionoverpotential terms, and assuming no activation overpotential, theelectrode potential is a measure of the surface lithium activity. Thefirst cathodic feature is the rapid increase in current at ˜330 mV that,according to room temperature data⁷, corresponds to the presence ofLi₁₂Si₇. The lowest potential reached is 25 mV and this is taken to beassociated with the presence of higher Li compounds, e.g. Li₂₁Si₅. Thecycling sequence shows a progressive “activation” of the sample,associated with increasing breakdown of the crystalline siliconstructure (see discussion). The anodic, part of the CV curve isassociated with progressive de-lithiation of the electrode according tothe various ZPC equilibrium potentials. For a scan rate of 1 mVs⁻¹ thecapacity (260 mAhcm⁻²) of the electrodes is roughly comparable to thepillar volume being converted to Li₁₂Si₇, while for the slower scanrates the capacity exceeds that of the pillar volume. The latter resultspoint to the participation of the substrate in the alloying/de-alloyingprocess.

FIG. 3 shows the results for a series of galvanostratic measurements onstructured Si at two different charge/discharge current densities(details in caption).

FIG. 4 shows the structure of the K-series of silicon electrodes thatwere used in this study and the effects of extensive galvanostaticcycling upon that structure. The structure are clearly intact, but atthe higher current density slight cracking of the bulk Si surface, belowthe pillars, is observed.

FIG. 5 shows the SEM pictures of the structures obtained on planar(un-pillared) Si electrodes before cycling and, separately, aftergalvanostatic cycling. When cycled at the lower current densities, thesurface is deformed, though crack formation does not occur. Cycling athigher current densities produces wide cracks.

REFERENCES

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1. A method of fabricating an energy storage device comprising the stepsof: forming an anode comprising an array of sub-micron siliconstructures supported on a silicon substrate; forming a cathodecomprising lithium; and arranging the anode and cathode in communicationto form a battery.
 2. A method of fabricating a device according toclaim 1 in which the anode is arranged to tolerate the conditionsoccasioned by the volume changes caused by charging/discharging of thebattery.
 3. A method according to claim 1 in which the anode is arrangedto maintain structural integrity throughout a cycling of the battery. 4.A method according to claim 1 in which the anode is arranged towithstand repeated volume expansion associated with alloying during useof the battery.
 5. A method according to claim 1 wherein the step offorming the array of submicron silicon structures comprises forming anarray of sub-micron silicon pillars.
 6. A method according to claim 5wherein the step of forming the pillars comprises forming pillars havinga surface area of about 4 FH/d times the substrate area wherein F is thesurface fractional coverage, H is the height of the pillar and d is thediameter of the pillar.
 7. A method according to claim 5 furthercomprising the step of arranging the sub-micron pillars to not exceed afractional coverage of 0.5 of the substrate.
 8. A method according toclaim 5 wherein the step of forming the pillars comprises formingpillars which are 0.1 to 1.0 microns in diameter and 1 to 10 microns inheight.
 9. A method according to claim 5 wherein the step of forming thepillars comprises forming pillars which are approximately 0.3 microns indiameter and approximately 6 microns in height.
 10. A method accordingto claim 1 wherein the sub-micron silicon structures are formed on asubstrate comprising n-type silicon.
 11. A method according to claim 1comprising forming the energy storage device on a wafer-bondedsilicon-on-insulator substrate.
 12. A method of operating a battery,including a silicon anode comprising an array of sub-micron siliconpillars on a silicon substrate and a lithium cathode, the methodcomprising the step of forming a compound film on the silicon pillarsduring a charging step.
 13. A method according to claim 12 wherein thefilm is a Zintl-Phase Compound.
 14. A method according to claim 12wherein the step of forming the compound film comprises forming adeformable compound film which does not to give rise to significantstress-induced cracking during the volume change in a charging ordischarging step of the battery.
 15. A method of fabricating anelectrode to form a battery with a lithium cathode and a lithium-basedelectrolyte comprising forming sub-micron silicon pillars on a siliconsubstrate.
 16. A method according to claim 1 further comprising thesteps of forming the sub-micron silicon structures on a siliconsubstrate, the steps comprising: (a) depositing a thin film of cesiumchloride onto a silicon based substrate; (b) exposing the film to watervapour so that the film reorganizes into a distribution of hemisphericalislands on the surface; and (c) reactive ion etching the coatedsubstrate, with the islands of cesium chloride acting as a resist sothat the uncoated silicon is etched away leaving the sub-micron siliconstructures on the surface of the substrate.
 17. A method according toclaim 1 wherein the step of forming the array of sub-micron structuressupported on a silicon-based substrate, comprises: (a) depositing a filmof a soluble solid onto the silicon-based substrate; (b) exposing thefilm to solvent vapour so that the film reorganises into an array ofdiscrete hemispherical islands on the surface; and (c) reactively ionetching the silicon-based substrate with the islands of highly solublesolid acting as a resist so that the exposed silicon-based substrate isetched away leaving sub-micron silicon structures corresponding to theislands.